1. Field of the Invention
This invention relates to the testing of microprocessors and cache memory subsystems and more particularly to techniques for testing processor cache coherency in the presence of external snoops.
2. Description of the Relevant Art
Cache-based computer architectures are typically associated with specialized bus transfer mechanisms to support efficient utilization of the cache memory and to maintain data coherency. A cache memory is a high-speed memory unit interposed in the memory hierarchy of a computer system between a slower system memory and a processor core to improve effective memory transfer rates and accordingly improve system performance. The name refers to the fact that the small cache memory unit is essentially hidden and appears transparent to the user, who is aware only of a larger system memory. The cache is usually implemented by semiconductor memory devices having speeds that are comparable to the speed of the processor, while the system memory utilizes a less costly, lower-speed technology. The cache concept anticipates the likely reuse by the microprocessor of selected data in system memory by storing a copy of the selected data in the cache memory.
A cache memory typically includes a plurality of memory sections, wherein each memory section stores a block or a "line" of two or more words of data. For systems based on the particularly popular model 80486 microprocessor, a line consists of four "doublewords" (wherein each doubleword comprises four 8-bit bytes). Similarly, in the equally popular AMD.sub.K 86.TM. processor, a line consists of eight doublewords. Each line has associated with it an address tag that uniquely identifies which line of system memory it is a copy of. When a read request originates in the processor for a new word (or a new doubleword or a new byte), whether it be data or instruction, an address tag comparison is made to determine whether a copy of the requested word resides in a line of the cache memory. If present, the data is used directly from the cache. This event is referred to as a cache read "hit". If not present, a line containing the requested word is retrieved from system memory and stored in the cache memory. The requested word is simultaneously supplied to the processor. This event is referred to as a cache read "miss".
One aspect that affects system performance and design complexity is the handling of writes initiated by the processor or by an alternate bus master. Because two copies of a particular piece of data or instruction code can exist, one in system memory and a duplicate copy in the cache, writes to either the system memory or the cache memory by the processor or an alternate bus master can result in an incoherence between the two storage units. Thus, a cache coherency protocol is typically implemented by the system in order to maintain cache coherence.
One popular cache coherence protocol is referred to as the "MESI" protocol. A line in a cache subsystem implementing the MESI protocol may acquire one of four states: Modified, Exclusive, Shared, or Invalid. FIG. 1 is a table that illustrates possible cache line state transitions due to processor read and write operations in an exemplary processor implementing the MESI protocol. The table further illustrates whether a writethrough or writeback operation is effectuated. FIG. 2 is a table that illustrates possible cache line transitions due to snoop, invalidation, and replacement cycles.
The test of a microprocessor's functionality is essential in determining whether a particular processor has any design or manufacturing defects. While upon first consideration the test of the coherency operations of a cache subsystem in a microprocessor might appear to be simple confirmation of the states of a particular cache line before and after a particular cache access, complicated timing analysis may actually be required due to the various stages of buffering in a pipelined processor through which a particular operation must progress. A defect at any point in the cache subsystem pipeline stages can cause a fatal and difficult-to-detect error in the system. Particularly, since an external snoop may occur at any point during the effectuation of a memory operation associated with the cache memory, a separate test must be performed to determine proper cache operation for each possible stage through which the operation may have progressed at the point when the external snoop occurs. Such tests are highly dependent upon the timing, the routing, and the pipelining associated with the specific processor and cache subsystem being tested.
A particular problem occurs when a processor design is revised, such as when modifications are made to a processor to allow higher frequencies of operation. Frequently, when the processor is modified the timing associated with cache memory operations may be changed, for example, through the addition or deletion of various pipeline stages or through a change in the ratio of the internal to external clock frequencies. When such modifications are made, the test routines created for the previous version of the processor may become invalid or, perhaps even worse, may omit essential tests upon certain aspects of the subsystem. As a result, processor malfunctions may go undetected, and substantial time and effort must be devoted to creating new test routines for the revised processor.
It would accordingly be desirable to provide a cache coherency test apparatus and methodology for testing cache coherency in the presence of external snoops wherein timing and architectural dependencies associated with the test routines may be reduced.